The present invention relates to driver circuits for high-speed data communication systems and, particularly, to source-series terminated (SST) drivers.
Source-series terminated (SST) drivers are versatile building blocks in multi-standard I/O transmitters thanks to their low-power operation, their low area consumption, their full CMOS implementation capability and their flexible termination characteristics. Moreover, the SST drivers support both single-ended output and differential operation.
Usually and as exemplarily disclosed in Document C. Menolfi et al., “A 16 Gb/s source-series terminated transmitter in 65 nm CMOS SOI”, ISSCC, Digital Technical Papers, pp. 446-447, February 2007, in order to achieve a robust high-speed operation, a multiplexer is incorporated into the driver that is switched to combine two half-rate data streams to one full-rate output signal.
At high transmission speeds, the performance of existing driver circuits is limited due to nodal charges in the stacked transistor arrangement of the output driver. These charges strongly depend on the transmission history and hence cause a data-dependent timing jitter (intersymbol interference).
For example, in document U.S. Pat. No. 7,511,530 B1 an SST half-rate driver is disclosed having an additional circuitry for minimizing data-dependent jitter and for increasing the frequency amplitude. In order to improve high-speed characteristics, the additional circuitry includes additional discharge switches which are introduced in the driver to effectively reset the nodal charges to zero. The discharge switches are operated to discharge a node in the driver output stage for the purpose of removing the stored charge prior to the next transition cycle of the output stage.
This solution, however, has higher power consumption for driving the additional switches and may add an additional parasitic capacitance at critical internal driver nodes that would limit the achievable data transmission speed.